In previous DDR-DRAM semiconductor memories, the individual semiconductor memory components were supplied with the data, address and control signals as well as clock signals via separate bus line systems in each case. The read and write data was normally transmitted bi-directionally using a specific number of parallel data bits.
As a result of the considerably higher transmission rates (up to 7.2 Gbits/s per pin), data signals as well as address and control signals, and the clock signals as well, will be transmitted via differential signal lines in the next generation (for example DDR4 and NMT (New Memory Technology)) of DDR-DRAM memories that are currently being developed. For this reason, the number of pins for these signals would have to be at least doubled for the conventional architecture of memory transmitting and receiving interfaces. However, such an increased number of pins is neither desirable nor possible, either for the individual memory components (chips) or for the memory modules on which they are mounted.
In order to reduce the number of pins and, since the data, control and address signals will be transmitted unidirectionally in the next memory generation, new transmitting and receiving interface circuits are being developed which will transmit and receive the data, control and address signals to be transmitted within one frame (signal frame), that is to say in each case matching a transmitting and receiving protocol and complying with very strict time conditions. These signals will likewise, of course, be transmitted differentially, with the clock signal being transmitted separately. Protocol-oriented transmitting and receiving interface circuits such as these require high-speed coding and decoding logic in the transmitting and receiving section of the memory interface, with data and clock preprocesssing being required in the receiving section.
In order to combine the data bits which are read from the memory arrays and are to be transmitted to form a data stream which matches the protocol, the transmitting part of the memory interface requires parallel/serial conversion, which converts the data which is read in a parallel form comprising a plurality of bits from the memory arrays, to a serial one-bit data signal stream in synchronism with the clock signal.